This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to an integrated redundancy architecture system for an embedded DRAM (eDRAM) macro system having a wide data bandwidth and wide internal bus width.
Embedded DRAMs (eDRAMs) with wide data bandwidth and wide internal bus width have been proposed to be used as L2 (level-2) cache to replace pure SRAM cache. Since each DRAM memory cell is formed by a transistor and a capacitor, the size of DRAM cache is significantly smaller than that of SRAM cache. In order to meet performance requirements, DRAMs are made of a plurality of blocks or micro-cells. A block is a small DRAM array unit formed by a plurality of wordlines (e.g., from 64 to 256) and a plurality of bitline pairs (e.g., from 64 to 256). The size of a block is much smaller (e.g., 16xc3x97 to 256xc3x97) than that of a bank of a conventional stand-alone DRAM. Only one block of the eDRAMs is activated each time. The read and write speed of an eDRAM can be fast due to very light loading of wordlines and bitlines.
In order to effectively utilize the large DRAM cache size, a small SRAM unit about the same size of an eDRAM block is used. The SRAM unit serves as a cache interface between an eDRAM and processor(s). The wide internal bus is used for transferring data among eDRAM, SRAM and the processor(s). More specifically, data residing in eDRAM memory cells coupled to a wordline traversing an eDRAM block is transferred to primary sense amplifiers. The data is then transferred to corresponding secondary sense amplifiers. The data is then transferred to the SRAM and stored in the memory cells thereof at the same wordline location. A TAG memory records the block address of the data stored within the SRAM. The data is then transferred to the processor(s).
Generally, neither column addressing nor column decoding is provided for the wide bandwidth eDRAM configuration, since they are not necessary. Hence, a main challenge of the wide bandwidth eDRAM configuration is to provide an effective column redundancy scheme to repair defective column elements without using column addressing. Most of the conventional DRAM approaches require a column address to indicate the location of failed column elements requiring repair.
In a conventional DRAM array, bitline pairs are grouped hierarchically by column address. Only one data bit from a group of bitlines is selected to be transferred via the local and global datalines each time. Therefore, the most common redundancy approach for the conventional DRAM is to provide repair for whole group of bitlines using the column address.
This approach does not lend itself to a wide bandwidth eDRAM, because data from every pair of bitlines of the eDRAM is simultaneously accessed. Further, since all the datalines are coupled to the eDRAM, the data from every pair of bitlines is simultaneously transferred to SRAM cache; and since all the datalines are coupled to the SRAM, the data from the SRAM is then all simultaneously transferred to the processor(s). For such a one-to-one wiring configuration, if any of the datalines fail and no redundancy is offered, the chip must be discarded.
If, however, redundancy bitlines are provided in the wide bandwidth eDRAM, it is not easy to correctly replace the failed pair of bitlines without affecting the integrity of the data flow pattern. This is because any defective column or row element must be replaced dynamically within each clock cycle with corresponding redundant elements without breaking data flow pattern. Further, the dynamic redundancy replacement process and the redundant elements themselves should not add any extra delay in the critical path of data flow. Due to these requirements, such in-situ redundancy replacement process must be performed in nanosecond speed. Accordingly, an integrated redundancy architecture system is needed which meets the speed requirement of an eDRAM macro without adding too much complexity to the DRAM system.
An aspect of the present invention is to provide an integrated redundancy architecture system for an embedded DRAM (eDRAM) macro system having a wide data bandwidth and wide internal bus width.
Another aspect of the present invention is to provide an integrated redundancy architecture system for an eDRAM macro system capable of efficiently storing fuse column and row information, in order for the information to be quickly retrieved during each cycle of eDRAM operation to provide an SRAM-like operation.
Further, another aspect of the present invention is to provide an integrated redundancy architecture system which provides redundancy operation to fulfill simultaneous eDRAM read/write operations.
Finally, another aspect of the present invention is to provide an integrated redundancy architecture system for an eDRAM macro system having a minimum amount of redundancy hardware for minimizing the amount of chip area utilized by the system.
Accordingly, an integrated redundancy eDRAM architecture system for an embedded DRAM macro system having a wide data bandwidth and wide internal bus width is disclosed which provides column and row redundancy for defective columns and rows of the eDRAM macro system. Internally generated column and row addresses of defective columns and rows of each micro-cell block are stored in a memory device, such as a fuse bank, during an eDRAM macro test mode in order for the information to be quickly retrieved during each cycle of eDRAM operation to provide an SRAM-like operation. A column steering circuit steers column redundant elements to replace defective column elements. Redundancy information is either supplied from an SRAM fuse data storage device or from a TAG memory device depending on whether a read or write operation, respectively, is being performed. The integrated redundancy eDRAM architecture system enables data to be sent and received to and from the eDRAM macro system without adding any extra delay to the data flow, thereby protecting data flow pattern integrity.